70 -- 70 -- RADIATION HARDENED SINGLE BOARD SPACE COMPUTERS

Notice Date

August 9, 2001

Contracting Office

Department of the Navy, Office of Naval Research, Naval Research Laboratory/STENNIS, John C. Stennis Space Center, Stennis Space Center, MS, 39529-5004

ZIP Code

39529-5004

Solicitation Number

N00173-01-R-RS03

Response Due

August 30, 2001

Point of Contact

Richard Sewell, Contract Specialist, Phone 228-688-4571, Fax 228-688-6055, Email rsewell@nrlssc.navy.mil -- Patricia Lewis, Contracting Officer, Phone 228-688-5593, Fax 228-688-6055, Email plewis@nrlssc.navy.mil

Description

This is a combined synopsis/solicitation for commercial items prepared in accordance with the format set forth in Federal Acquisition Regulation, Subpart 12.6, as supplemented with additional information included in this notice. This announcement constitutes the only solicitation; proposals are being requested and a written solicitation will not be issued. This solicitation is issued as Request for Proposal (RFP) Number N00173-01-R-RS03. This solicitation document and incorporated provisions and clauses are those in effect through Federal Acquisition Circular 97-27 and DFARS Change Notice 20001213. This synopsis/ solicitation is issued on an unrestricted basis and is open to all interested parties. The associated NAICS code is 336419 with a small business size standard of 1,000 employees. DESCRIPTION: CONTRACT LINE ITEM NUMBER (CLIN) 0001: The Government has a requirement for RADIATION HARDENED SINGLE BOARD SPACE COMPUTER(S) (SBSC) to be used on the Sun Earth Connection Coronal and Heliospheric Investigation (SECCHI) that is being prepared for launch on the NASA/STEREO spacecraft. The Offeror shall propose a quantity of 2 unit(s) for initial delivery and an additional 1 optional unit. The SBSC shall, as a minimum, contain the following functional components: a radiation-hardened central processing units (CPU), a bridge to a Compact PCI interface, startup read only memory (SUROM), and local memory. The requirements for each of these components are addressed hereafter: (1) The CPU shall, as a minimum, possess the following characteristics and functionality: (a) an instruction set that is functionally and operationally compatible with both the VxWorks operating system and a Power PC instruction set architecture; (b) a hardware floating point unit that implements the IEEE-754 floating point standard; (c) 32 Kilobytes of instruction cache; (d) 32 Kilobytes of data cache; (e) software-controlled power savings modes of full power, 1/2 power, and 1/4 power; and (f) an L2 cache interface internal to the SBSC which supports at least 1 Megabyte of cache addressability. (2) The Bridge/Compact PCI Interface shall, as a minimum,(a) provide an interface between the CPU native bus and a Version 2.1 compatible PCI bus; (b) support PCI burst mode with continuous data transfers; (c) provide PCI arbitration and resource control; (d) provide a memory data and address interface; (e) provide multiple bit memory error detection and single bit error correction (EDAC) on the SUROM and local RAM that is enabled on reset; (f) provide visibility into the number and associated address of memory corrections; (g) perform an automatic memory scrub; (h) perform cache snooping on system memory accesses; (i) provide a 16550 compatible UART interface; (j) provide CPU, PCI and JTAG clock control; (k) provide three programmable timers; (l) provide operating system tick and cycle start interrupts; (m) provide a watchdog timer; (n) provide interrupts and discretes; (o) control DMA operation; (p)provide power savings modes to match the CPU power savings modes; (q) provide dual JTAG master interfaces; (r) provide JTAG tap controller; and (s) support non-maskable and software maskable interrupts. (3) The SUROM on the SBSC board shall, as a minimum, possess the following characteristics and functionality: (a) a minimum of 256 Kilobytes of non-volatile EEPROM; (b) The EEPROM shall support the initial CPU program load on initial power-up; (c) The SUROM shall be organized as 128K x 24 with 16 bits of data and 8 bits of error detection code; (d) The error detection code shall provide single bit error correction and double bit error detection; and (e) All SUROM shall be directly addressed by the CPU and by any internal master function of the Compact PCI bus. (4) The Local Memory on the SBSC board shall, as a minimum, possess the following characteristics and functionality: (a) A total of 128 MBytes of synchronous DRAM shall be provided on the SBSC; (b) The memory shall be directly addressable by the CPU and by any internal master function of the Compact PCI bus; (c) The memory shall be organized as 16M x 80 with 64 bits of data and 16 bits of error correction code; (d) The error correction code shall provide single nibble error correction and double nibble error detection; and (e) The memory shall support being placed into a self-refresh mode by software control to enable its memory contents to be retained during a reset or any duration. During this mode, the SDRAM will not need to be scrubbed for single bit errors. Physical, functional, and performance requirements for the system as a whole are as follows: (a) The SBSC shall be capable of operating at a rail temperature of 70 degrees centigrade; (b) The CPU processing speed shall be at least 240 Dhrystones (V2.1) when the CPU is operating at a clock speed of 133 MHz; (c) The SBSC weight shall be less than 550 grams; (d) Typical power dissipation for the SBSC shall be less than 12 Watts; (e) The card size shall be 3U (100mm x 160mm); (f) The SBSC shall be capable of surviving a total dose of 100 Krad (SI) and be immune to latchup. The Single Event Upset (SEU) rate shall be less than 1E-5 upsets/day at a radiation rate consistent with geosynchronous earth orbits (GEO); (g) Performance for the required system shall meet or exceed 5.8 SPECint95 and 3.3 SPECfp95 at a clock speed of 133 MHz; (h) Mean time between failures shall exceed 390,000 hours; (i) The SBSC shall be capable of operating from an input voltage of 3.3 V +/- 10%; (j) The Compact PCI backplane bus shall be 32 bit, 33 MHz, PCI Version 2.1; (k) The peak bandwidth of the PCI bus shall support 130 MB/s write and 90 MB/s read. The successful Contractor shall perform standard acceptance testing appropriate for space flight prior to shipment. The successful Contractor shall propose test procedures and limits for the Government's review prior to testing. The successful Contractor shall also provide the Government with (a) As-Built Manufacturing Records and Test Results with the SBSC units upon delivery; (b) Start-up ROM and a VxWorks Board Support Package; and (c) Hardware reference manuals and a software user?s guide in both hardcopy and electronic media. The required SBSC systems shall be a fully functional, fully operational, fully integrateable systems. For the purpose of this solicitation, a fully functional, fully operational, fully integrateable system is defined as a family of sub-elements (materials, parts, assemblies and subassemblies, components and subcomponents, hardware, software, firmware, etc.,) which, when assembled, form an integrated complex whole that is structured so that its constituent parts perform in a functionally and operationally compatible manner. All items shall be delivered FOB Destination not later than nine (9) months after award. Delivery/Acceptance point is Naval Research Laboratory, Code 7601 ATTN: Richard M. Rubin, Bldg 209, Rm 123, 4555 Overlook Ave, Washington DC 20375-5320. Government workdays are Monday through Friday between the hours of 0800 and 1630 local time. The solicitation and incorporated provisions and clauses are those in effect through Federal Acquisition Circular 97-27 and DFARS Change Notice 20001213. The FAR and DFARS provisions and clauses are hereby incorporated by reference. For full text of FAR and DFARS provisions and clauses see http://farsite.hill.af.mil/. Offerors are advised to propose in accordance with the provision at FAR 52.212-1, Instructions to Offerors -- Commercial Items (OCT 2000). Offerors will be evaluated in accordance with FAR 52.212-2, Evaluation -- Commercial Items (JAN 1999). The specific evaluation criteria to be included in paragraph (a) of FAR 52.212-2 are: (1) technical capability of the item offered to meet the Governments minimum needs based on examination of product literature or technical approach narrative, (2) Past Performance [see FAR 52.212-1(b)(10)] and (3) Price. Technical Capability and Past Performance, when combined are of greater importance than Price. Offerors are also advised to include with their offer a completed copy of the following provisions: FAR 52.212-3, Offeror Representations and Certifications -- Commercial Items (MAY 2001); DFARS 252.212-7000 Offeror Representations and Certifications?Commercial Items (NOV 1995); and DFARS 252.225-7000, Buy American Act/Balance of Payments Program Certificate. The clause at 52.212-4, Contract Terms and Conditions-Commercial Items (MAY 2001), applies to this acquisition. The addenda to the clause are (1) YEAR 2000 COMPLIANT INFORMATION TECHNOLOGY This requirement applies to information technology (IT) that processes date-related information. All such IT delivered under this contract shall be Year 2000 compliant as defined at FAR 39.002. (2) REQUIREMENTS FOR ON-SITE CONTRACTORS For any portion of work under this contract performed at any NRL site, the Contractor shall comply with the Requirements for On-Site Contractors dated 08 DEC 2000, which are hereby incorporated by reference. The document entitled Requirements for On-Site Contractors may be found in full text at: http://heron.nrl.navy.mil/contracts/home.htm. The following FAR clauses also apply to this acquisition: FAR 52.211-6, Brand Name or Equal, FAR 52.212-4, Contract Terms and Conditions -- Commercial Items and FAR 52.212-5 Contract Terms and Conditions Required to Implement Statues or Executive Orders -- Commercial Items. The additional clauses cited under FAR 52.212-5 that are applicable to this acquisition are: FAR 52.203-6 entitled Restriction on Subcontractor Sales to the Government, with its Alt I; FAR 52.203-10 entitled Price or Fee Adjustment for Illegal or Improper Activity; FAR 52.219-4 entitled Notice of Price Evaluation Preference for HUBZone Small Business Concerns; FAR 52.219-8 entitled:Utilization of Small Business Concerns;, FAR 52.219-14 entitled: Limitations of Subcontracting; FAR 52.222-26 entitled Equal Opportunity; FAR 52.222-35 entitled Affirmative Action for Disabled Veterans and Veterans of the Vietnam Era; FAR 52.222-36 entitled Affirmative Action for Workers with Disabilities; FAR 52.222-37 entitled Employment Reports on Disabled Veterans and Veterans of the Vietnam Era; and FAR 52.232-33 entitled Payment by Electronic Funds Transfer-Central Contractor Registration. The clause at DFARS 252.212-7001, Contract Terms and Conditions Required to Implement Statutes or Executive Orders Applicable to Defense Acquisitions of Commercial Items, applies to this acquisition. The additional clauses cited under DFARS 252.212-7001 that are applicable to this acquisition are: DFARS 252.204-7004, 252.225-7001, 252.225-7012, 252.227-7015,252.227-7037 and 252.233-7000. The following clause is also applicable to this solicitation: Electronic and Information Technology (EIT). In accordance with Section 508 of the Rehabilitation Act of 1973 (29 U.S.C. 794d), all EIT supplies and services provided under this contract must comply with the applicable accessibility standards issued by the Architectural and Transportation Barriers Compliance Board at 36 CFR part 1194 (see FAR Subpart 39.2). Electronic and information technology (EIT) is defined at FAR 2.101. PROPOSAL PREPARATION INSTRUCTIONS: The Offeror shall clearly demonstrate how all proposed products meet the requirements set forth herein and shall also provide a minimum of 3 references to which the same or similar products have been delivered within the last 2 years. References shall include the product/services delivered, contract number, date of contract award, date of acceptance by the receiving organization, contracting office point of contact, technical office point of contact, current telephone and fax numbers for both and statement regarding problems with the product, contract and/or delivery. The Government will only consider the information provided in the offeror's proposal. It is anticipated the award will be made without discussion; therefore each offeror is encouraged to submit their best terms with their proposal. Failure to submit the information set forth herein for evaluation may render the offer nonresponsive. Each offeror is also encouraged to provide supplemental documentation to support the realism and reasonableness of their proposed cost/price. The applicable Defense Priorities and Allocations System (DPAS) rating for this solicitation and any resulting contract is DO-A7. The Contractor shall follow all of the requirements of this regulation. Offers shall be delivered to Procuring Contracting Officer Code 3235:RDS, Naval Research Laboratory, Department of the Navy, Stennis Space Center, MS 39529-5004 and received no later than 3:30 p.m. C.S.T. 30 AUG 2001. The package should be marked: RFP N00173-01-R-RS03, Closing Date: 30 AUG 2001. For information regarding this solicitation contact Richard D. Sewell, Contract Specialist, at (228)688-5784. All responsible sources responding to this solicitation will be considered. All information and requirements associated with this acquisition are contained solely in the synopsis/solicitation.

Web Link

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Record

Loren Data Corp. 20010813/70SOL009.HTM (D-221 SN50U574)