A -- RESEARCH AND DEVELOPMENT

Notice Date

November 14, 2000

Contracting Office

Defense Microelectonics Activity(DMEA), Directorate of Contracting/MEOP, 4234 54th Street, Bldg 620, McClellan AFB, CA 95652-1521

ZIP Code

95652-1521

Solicitation Number

DMEA90-01-R-0002

Response Due

November 30, 2000

Point of Contact

Contracting Officer, Kellie Valdez, 916 643-2245

E-Mail Address

Contracting Officer (valdez@dmea.osd.mil)

Description

Item 0001: ENGINEERING SERVICES. Quantity: 1 Lot. Del to DMEA/METD 4234 54th Street, McClellan, CA, 95652-2100. Duration: 2/1/01 through 2/28/06; The objective of this acquisition is to develop, implement, and demonstrate a sub-micron, radiation hardened UTSi manufacturing process for use within the Defense Microelectronics Activity (DMEA) Flexible Foundry. The UTSi process development will provide a cost effective solution for the DMEA design and fabrication capability required for the manufacturing of military and space qualified radiation hardened integrated circuits used to support the DMEA mission. This project is one part of a major research and development program at DMEA which incorporates many interrelated and interdependent projects. The contractor shall develop, implement, and demonstrate the functionality of the DMEA Flexible Foundry UTSi process. The contractor shall deliver process licenses, UTSi design, simulation, and layout libraries, full flow and partial mask sets, and fabricated wafers. Process Development: The contractor shall develop and deliver the items required to transfer the UTSi process to the DMEA Flexible Foundry, including but not limited to,:- Sapphire Wafer Specification- Sapphire Wafer Thinning Process Description- Epitaxial Silicon Deposition Specification- Improvement Process Description- UTSi Spice Files- UTSi Process Description- UTSi Process Control Monitor Description- UTSi Design Rules- UTSi Process Simulations- Description of Design Considerations for Covering Bulk Designs to UTSi -- Description of ESD Protection Devices for SOI Integrated Circuits. Process Transfer: The contractor shall transfer the UTSi process to the DMEA Flexible Foundry. The contractor shall provide engineering and technical support during development efforts.Transfer Study: The contractor shall evaluate the DMEA Flexible Foundry equipment, manpower, and facility. Based upon the results of the evaluation, the contractor shall recommend the enhancements required to implement the UTSi process delivered under paragraph 3.1 of this SOW. These recommendations shall be in the areas of equipment, manpower, chemicals and gasses, facility space, safety, environmental, and any other that the contractor deems relevant. Upper Layer Process Implementation: Upon DMEA completion of the enhancements identified in the study under paragraph 3.2.1 of this SOW, the contractor shall implement the upper layer processing capability in the DMEA Flexible Foundry. This shall include two (2) partial mask sets and 24 wafers split into four (4) sublots of six (6) wafers. Underlayer Process Implementation: Upon completion of the upper layer process implementation identified under paragraph 3.2.2 of this SOW, the contractor shall implement the underlayer processing capability in the DMEA Flexible Foundry. The contractor shall deliver two (2) full flow mask sets and 24 wafers split into two (2) sublots of six (6) wafers and one (1) sublot of twelve (12) wafers. Process verification: The contractor shall verify the capabilities of the UTSi process installed in the DMEA Flexible Foundry. The contractor shall fabricate three (3) Application Specific Integrated Circuits (ASIC) in their foundry to use as "gold standard" comparison components. The Contractor shall fabricate a PGKP ASIC, FPGA ASIC, and CPU ASIC. The contractor shall deliver a full flow mask set and twelve (12) wafers for each ASICfabricated to DMEA for corresponding verification fabrications in the Flexible Foundry. The contractor and DMEA shall compare the functionality of the three (3) externally fabricated ASICs to the functionality of the same ASICs fabricated using the UTSi process in the DMEA Flexible Foundry. The contractor shall support process adjustments, if required to match the Flexible Foundry results with the Peregrine foundry results. Justification for noncompetitive action: This is a sole source procurement to Peregrine Semiconductor Corporation, Melbourne FL 32901. Intended Source(s): For subcontracting opportunities contractor's may contact the above Contract. See Numbered Note(s) 22, 26

Record

Loren Data Corp. 20001116/ASOL001.HTM (W-319 SN5066A0)