Loren Data Corp.

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COMMERCE BUSINESS DAILY ISSUE OF OCTOBER 6,1998 PSA#2195

NASA/Goddard Space Flight Center, Code 215, Greenbelt, MD 20771

59 -- SILICON-ON-INSULATOR (SOI) BONDED WAFERS SOL 553-94040-920 DUE 102398 POC Mary E. McKaig, Contract Specialist for Simplified Acquisition, Phone (301) 286-4240, Fax (301) 286-1720, Email Mary.E.McKaig.1@gsfc.nasa.gov WEB: Click here for the latest information about this notice, http://nais.nasa.gov/EPS/GSFC/date.html#553-94040-920. E-MAIL: Mary E. McKaig, Mary.E.McKaig.1@gsfc.nasa.gov. NASA/GSFC plans to issue a Request for Quotation (RFQ) for the purchase of 200 silicon-on-insulator (SOI) bonded wafers. This procurement is being conducted under the Simplified Acquisition Procedures (SAP). NASA/GSFC intends to purchase the items from SOITEC/USA in Peabody, MA. Extensive market research has revealed SOITEC/USA as the only company to meet all requirements/specifications. The Government intends to acquire a commercial item using FAR Part 12. Any referenced notes can be viewed at the following URL: http://genesis.gsfc.nasa.gov/nnotes.htm. Interested firms have 15 days from the publication of this synopsis to submit in writing to the identified point of contact, their qualifications/capabilities with respect to provide such items. Such qualifications/capabilities will be used solely for the purpose of determining whether or not to conduct this procurement on a competitive basis. Responses received after the 15 days or without the required information will be considered nonresponsive to the synopsis and will not be considered. A determination by the Government to not compete this proposed effort on a full and open competitive basis, based upon responses to this notice is solely within the discretion of the Government. Oral communications ARE NOT acceptable in response to this notice. All responsible sources may submit an offer which shall be considered by the agency. An Ombudsman has been appointed. See Internet Note "B". Interested firms who feel they can submit a qualifications/capabilities statement must demonstrate in their response how they can meet the following specifications: Wafers shall be composed of single-crystal silicon wafers, bonded together with a silicon dioxide interface. The silicon dioxide shall be thermally grown and defect free. The top layer silicon (henceforth referred to as the device wafer) shall be of excellent quality single-crystal silicon and shall be free of gross defects as observed by the XTEM method. The front surface of the device wafer shall be polished to semiconductor standards according to the specifications which follow. The bottom layer silicon wafer (henceforth referred to as the handle wafer) shall be of excellent quality single-crystal silicon and shall be free gross defects as observed by the XTEM method. The back-side of the handle wafer shall be polished to semiconductor standards according to the specifications which follow. Specifications: 1) Device wafer: a) diameter: 100mm +/- 0.50 mm; b) thickness: 2.5 microns +/- 0.25 microns (range 2.25-2.75 microns); c) within wafer total thickness variation: 0.25 microns (maximum-minimum), as measured at 9 points across wafer; d) wafer-to-wafer total thickness variation: 0.25 microns, sorted and binned by thickness range; e) crystal orient. <100 > +/- 0.50 degrees; f) dopant: boron; g) resistivity: 14-22 ohm-cm, 15% ctr/10mm from edge; h) etch pit density: <2/square cm (HF), <1E4/sq. (Seeco); i) free of microbubbles and voids. 6mm (from edge) exclusion on device layer; j) polished. 2) Handle wafer: a) diameter: 100mm +/- 0.50mm; b) thickness: 381 microns +/- 15 microns; c) within wafer total thickness variation: 5 microns (maximum-minimum); d) wafer-to-wafer total thickness variation: 15 microns (maximum-minimum); e) crystal orient. <100 > +/- 0.50 degrees; f) crystal orientation with respect to device wafer: +/- 0.25 degrees; g) flats: SEMI standard <110 > +/- 0.50 degrees; h) dopant: boron; i) resistivity: 10.0-20.0 ohm-cm, 10% ctr/10mm from edge; j) polish: double side polish. 3) Buried silicon dioxide layer 1 (joining devide wafer and spacer wafer): a) thickness: 0.20 microns +/- 0.025 microns; b) pin hole density: <0.2/cm^2. 4) Laser mark: a) wafers shall be identified with unique serial numbers which include i) batch number, identifying the ingot of the starting material and the unique processing batch, and ii) a sequential counter for each wafer in the processing batch; b) the laser mark shall be located on the back-side of the handle wafer, near the wafer-flat. Certification: Each wafer shall be certified as to DEVICE wafer thickness, with thickness measured at 9 points across the wafer, excluding 5 mm from wafer edge. The certification report shall include: Total Thickness Variation (TTV) (measured as Maximum-Minimum), Maximum Thickness, Minimum Thickness, and Mean (Average of 9 measurements). Wafers shall be sorted and boxed according to Mean thickness. Wafer are to be appropriately double-wrapped for class-10, clean-room use. The total shipment of wafers shall be delivered no later than 20 weeks after receipt of order. Partial/earlier shipments will be accepted. Posted 10/02/98 (D-SN257941). (0275)

Loren Data Corp. http://www.ld.com (SYN# 0113 19981006\59-0001.SOL)


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