Commercial Acquisition Department, Bldg 11, Naval Undersea Warfare Center Division, Newport, Code 59, Simonpietri Dr., Newport, RI 02841-1708

70 -- DIGITAL SIGNAL PROCESSING BOARD SOL N66604-98-Q-5532 DUE 092298 POC J. Clermont, Contract Negotiator at (401) 832-1460; K. Hughes, Contracting Officer at (401) 832-1550; FAX (401) 832-4820. WEB: Naval Undersea Warfare Center Division, Newport, http://www.npt.nuwc.navy.mil/contract/. E-MAIL: J. Clermont, Contract Negotiator, clermontjm@npt.nuwc.navy.mil. An error occurred in the Description of CBD Notice, Submission No. 237206. This amends the Description. The Naval Undersea Warfare Center Division Newport, Newport, Rhode Island intends to procure Quantity (1) Digital Signal Processing Board comprised of a Motherboard with a mating PCI Mezzanine Card Daughterboard and Emulator Hardware/Software in accordance with Performance Specification requirements. A Supply type Purchase Order with Firm Fixed Price (FFP) provisions will be issued to the successful offeror. Award is based on low-cost technically acceptability. This is a combined synopsis/solicitation in accordance with the format in Federal Acquisition Regulation (FAR) Subpart 12.6, as supplemented with additional information included in this notice. This announcement constitutes the only solicitation; requests for quotations under N66604-98-Q-5532 are being solicited by this synopsis. A written solicitation will not be issued. This is in accordance with FAR Parts 12 and 13 Simplified Acquisition Procedures. Other applicable FAR Provisions are 52.212.1 Instructions to Offerors-Commercial Items, 52.212-2 Evaluation-Commercial Items (evaluation will be based on Technical Evaluation and Price), 52.212-3 Offeror Representations and Certifications-Commercial Items(will be requested before award), 52.212-4 and -5 Contract Terms and Conditions-Commercial Items, 52.211-14 Notice of Priority Rating for National Defense Use-This is a "DO" Rated Order and Defense Federal Acquisition Regulation Supplement (DFARS) 252.212-7001. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PERFORMANCE SPECIFICATION for a DIGITAL SIGNAL PROCESSING (DSP) BOARD: 1. SCOPE 1.1 Background Naval Undersea Warfare Center Division Newport, Newport, Rhode Island has been tasked to develop an acoustical signal processor, with an Asynchronous Transfer Mode (ATM) OC-3 fiber optic interface, for the East Coast Shallow Water Training Range (ECSWTR). This signal processor is implemented using an individual Versa Module Eurocard (VME) board,including (but not limited to) a SPARC (a RISC microprocessor) Processor Board and several individual Digital Signal Processor (DSP) Boards. The fiber-optic interface will be provided by a PCI Mezzanine Card (PMC) mated to one of the DSP boards. 1.2 Scope The requirements defined herein establish the minimum requirements for a DSP board along with its mating PMC Daughterboard. 2. APPLICABLE DOCUMENTS: 2.1 "ADSP-2106x SHARC (Super Harvard Architecture) User's Manual", Analog Devices, Inc., 2nd Ed., 7/96.(http://www.analog.com/). 2.2 Bellcore Documents * Synchronous Optical Network(SONET) Transport Systems: Common Generic Criteria, Issue 8, October 1993.(TA-NWT-000253) * Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria, Issue 2, December 1991 (TR-NWT-000253) * BISDN (Broadband Integrated Services Digital Network) UNI (User to Network Interface) and NNI (Network to Network Interface) Physical Layer Generic Criteria, Issue 1, June 1, 1993 (TR-NWT-000253) 2.3 ATM Forum Documents * ATM User-Network-Interface Specification, Version 3.0 September 10, 1993. * ATM Universal Test and Operations ATM-PHY (Physical layer) Interface Specification-Level 1, Version 2.01, February 1994. 3. REQUIREMENTS It is required that a Sharc 21060 DSP VME Motherboard W/PMC slot, an Interphase 4515 PMC ATM Adapter or equivalent, and a Sharc 21060 DSP HW/SW Emulator/Debugger be used. 3.1 VME Motherboard Characteristics & Configuration: * The VME motherboard shall be implemented on a single slot, 6U VME card. * The VME board shall be configured with a minimum of eight (8) Analog Devices ADSP-21060 digital signal processors, (DSP), operating at a minimum of 40 MHz. * The VME motherboard shall provide interrupt synchronization between processors. * The VME motherboard must be capable of beingreset from the front panel without resetting the VME bus backplane * The VME motherboard shall provide a fully compliant IEEE (Institute of Electrical and Electronic Engineers) P1386 PCI Mezzanine Card (PMC) slot. * The VME motherboard shall allow external synchronization with a pulse TTL (Transistor to Transistor Logic) waveform with a minimum pulse width of one microsecond. * The VME motherboard shall provide a JTAG scan path. * Each processor shall be equipped with a minimum of 128k 32-bit words (512k Bytes per processor or 4 Mbytes per board) of either dedicated, not dedicated or some combination of external Static Random Access Memory (SRAM). * Each processor must be accessible by individual processes running on the VME controller via VME. 3.2 Input/Output Characteristics & Configuration The following Fiber-Optic and Digital Input/Output capabilities must be implemented on the VME motherboard, PMC Daughterboard or any other attached daughterboard such that the single-width VME requirements statedabove is maintained: * The PMC Daughtercard shall be implemented on a single-width PCI Mezzanine. * The PMC Daughtercard shall provide a single mode SONET/ATM OC-3 fiber-optic interface (one input, one output) using SC connectors. The daughtercard must accept data using ATM Adaptation Layer (AAL) 0. * A bi-directional digital data path that provides a minimum of 80 M bytes per second must be provided from the VME P2 connector to the Sharc DSPs. 3.3 Development Software and Hardware/Software Support The vendor shall provide the following development software and emulation support: * Driver software compatible with Themis 5CE controller or equivalent operating Solaris 2.5 & above. * C/C++ callable library which includes standard control software allowing interruption and resetting of each ADSP-21060 independently, downloading of executable code and data, and uploading of data. * Hardware/software emulator for network based debugging. -- -- -- -- -- -- -- -- -- -- — -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Delivery will be F.O.B. Destination, Newport,RI, by 30 September 1998. All responsible sources may submit a proposal which shall be considered by the Government. The SIC Code for this procurement is 3577, 1,000 employees. This is 100% set aside for small business. Responses are due by 2:00 p.m. EDT 9/22/98; faxes may be sent to J.M.Clermont at 401-832-4820. Estimated RFP release date: 8/13/98. Posted 08/14/98 (W-SN237228). (0226)

Loren Data Corp. http://www.ld.com (SYN# 0369 19980818\70-0005.SOL)