Operational Contracts Division, Commodities Branch, AFDTC/PKOS, 205 West D Avene, Suite 541, Eglin AFB, FL 32542-6862

66 -- KINETIC-KILL-VEHICLE HARDWARE-IN-THE-LOOP SIMULATOR (KHILS) VACUUM COLD CHAMBER (KVACC) SOL F08651-98-Q-1134 DUE 042498 POC Paula Faye Cosson, (850) 882-5169, Contract Specialist; Kim D. Williams, Contracting Officer 17. The Air Force Development Test Center (AFDTC) is contemplating awarding a Sole Source procurement to Computer Science & Applications, 2 Clifford Dr, Shalimar, Florida, for a Kinetic-Kill-Vehicle Hardware-in-the-Loop Simulator (KHILS) Vacuum Cold Chamber's (KVACC) real-time infrared scene projection capability from single waveband to dual waveband. This requires the addition of one VME based Wideband Infrared Scene Projector (WISP) Array Control Electronics (WACE). This WACE converts real-time commands from a Night Hawk computer into addressing, synchronization, and 16-bit analog drive signals for commanding the infrared scene output of a WISP 512x512 resistive array. During real-time operation the WACE must support frame rates in excess of 100 HZ for the entire 512x512 array of pixels. The WACE also has a Bit-3 VME interface to a control console and 512Mbytes of memory for nonreal-time control during maintenance and unique array evaluations. Upgrading KVACC to a dual waveband capability requires that the WACE being procured be functionally compatible with the WACE currently integrated into the single waveband KVACC. Required delivery is to be within 60 days after contract award. Firms responding to this synopsis will be evaluated on their ability to remain compatible with the WACE which is housed in two VME chassis compatibility with the KHILS bus architecture, the Control Electronics Assembly and the Array Interface Electronics (AIE). The Control Electronics Assembly VME chassis must have total number of slots available must be 21 single width slots. The chassis must be configured for seven 6Ux160mm slots, with the remainder reserved for 9Ux400mm slots. The P1 and P2 backplanes must extend across the entire 21 slots for VMEbus compatibility with every board in the system. Three independent VSB overlays must be included to support independent, concurrent, high-speed, board-to-board transfer of pixel data. For compatibility with the KHILS real-time software the Control Electronics Assembly must use a Motorola MVME-162FX embedded processor board or functional equivalent to provide real-time control for existing KHILS Control Console. This includes the control of the image manipulation channels during a simulation. During a simulation the controller manages all KHILS Control Console board functions such as updating coefficients sent from a remote simulation computer and updating all control registers on all boards at each frame sync as necessary. The controller features a 32 MHz MC68040 32-Bit processor with memory management, 8 Kbytes of cache, a Direct Memory Access (DMA) controller, VMEbus support and 16 Mbytes of Dynamic Random Access Memory (DRAM). Also on board are two RS-232 serial interfaces, a parallel printer interface, an Ethernet interface and Small Computer System Interface (SCSI) -2 support. The Control Electronics Assembly must include a MVME712 interface which is a transition module used to support the use of standard I/O connectors for the MVME162 processor board. This interface takes theP2 backplane I/O connections from the peripherals on-board the MVME162 via ribbon cable to the transition module which reorganizes the signals into industry standard front panel connections (i.e. serial ports, parallel port, Ethernet port, etc.). The MVME712 interface occupies two slots in the VME chassis. The Control Electronics Assembly must include a VMEbus electronics subsystem to connect the user interface system (UIS) via a BIT3 Model 467 high speed bus link. This board set allows the two subsystems to share bus access with bi-directional random access bus mastering from either subsystem. The link provides a DMA controller for bi-directional 32-bit data transfers at rates up to 26 Mbytes per second. System drivers in the UIS allow simplified I/O through the adapter using standard operating system calls. The driver will automatically use DMA mode when possible to maximize throughput while maintaining minimum load on the UIS processor. The UIS uses this link for all memory to memory transfers between theUIS and the Control Electronics Assembly; the link is the primary means of communication between the two subsystems. All direct board initialization, as well bulk image downloading is performed through this link. The Control Electronics Assembly must include a frame store memory board to hold digitized imagery for playback to the scene projector as either a single frame of pixels or a sequence of many frames to form a prestored movie file. This board will be configured for 512 Megabytes of high speed, high density VME/VSB/VMEh4/VSB64 memory. The board must be upgradeable to 1 Gigabyte. The bus interfaces must conform to VMEbus Standard Revision D, and the VSB to Revision C. The read/write data rates of this memory board are dependent upon the bus master cycle times, but it will support the required 64 Megabytes per second rate for updating the scene projector in excess of 100Hz. Applications for this board include Non-Uniformity Correction (NUC) calibration, system diagnostics, and system demonstrations. TheArray Interface Electronics (AIE) must include a WISP Personality Board (WPB). This board manages the final pixel output from the Control Electronics Assembly to the AIE in terms of frame rate, pixel rate and Digital to Analog Converter (DAC) compensation. This board also has provisions for external synchronization with the Unit-under-Test (UUT) or other devices by means of front panel connectors to accept and/or source frame sync signals. The WPB is a VSB64 bus master capable of sustained data rates of 64Mbytes per second. The WACE frame rate shall be controlled in three different ways, depending upon the application. The simplest way is for software on the MVME162 processor board to issue "Go" commands to the frame sync logic at its own asynchronous rate. This mode is seldom used, except for board level checkout. The most common technique is to utilize the onboard programmable interval timer to automatically trigger the frame sync logic on precisely equal intervals from less than 1Hz to 120Hz with a resolution of 62.5ns. The third technique available is to enable an external source to apply a frame sync pulse, such as the UUT. The minimum external input pulse width is 100ns via a coaxial cable. The WAVE pixel rate shall be software programmable to support a variety of applications, such as NUC calibration, array characterization tests, or other types of resistor arrays. The programmable word rate formula is Word Rate = 8MHz/N, where N can vary from 1 to 15. A word is defined as four 16-bit pixels packed in a Big Endian 64-bit format. Normally, the value of N is set equal to 1. The WACE shall have several software programmable options provided for the scene playback mode of operation. In single frame mode, one frame only will be output to the array. Software intervention is required to repeat the output. In multiple frame mode, pixel data will be written to the array from the same VSB64 starting address at the system frame rate. The auto-repeat mode, frames from sequential VSB64 address space are written to thearray at the system frame rate. This mode applies only to the 64MB Frame Store Memory Board a planned future upgrade. The AIE must include DAC compensation logic is in the form of 32 programmable look-up tables (LUT), one for each 14-bit DAC channel. The application of these LUTs is summarized as modes a, b, and c below: a. DAC Channel Calibration. Pass-through look-up table entries are loaded to allow the DAC channels to be commanded uncompensated across their full 1-3.2 volt output range. The array must be disconnected during these procedures to prevent damage or unintentional annealing of the emitter resistor elements. The outputs of the DACs are read with a precision voltmeter to build a command vs. voltage response curve. From this data, DAC compensation tables are calculated for use in the array annealing procedures or normal array operation modes described below. b. Array Anneal Procedures. DAC limiting tables are loaded to allow the array to be commanded to the desired anneal voltage, but no higher. c. Normal Array Operation. DAC limiting tables are loaded to restrict the DAC channels to operate up to a predetermined level below the annealing voltage level, but no higher. In both modes b. and c. the LUT are also used to compensate for small DAC channel-to-channel differences to ensure that all channels produce the same output voltage from a given digital input command. Therefore, a DAC board could be replaced, if necessary, without the need to recalibrate the projector. Mode a. should not be necessary to repeat, as the DAC compensation tables and rescaling software will be provided with the delivered system. Technical questions may be directed to Robert Stockbridge, at (850) 882-4446 ext 2260. Contracting questions may be directed to Paula Faye Cosson at (850) 882-5169. Replies to this synopsis should be provided to AFDTC/PKOS, 205 West D Ave, Suite 541, Eglin AFB FL 32542-6862. All responsible sources may submit an offer which will be considered. (No contract award will be made on the basis of bids/proposals received in response to this synopsis.) Firms responding to this synopsis should reference F08651-98-Q-1134 and indicate whether they are or are not a small or small disadvantaged business concern as defined in FAR 52.219-1 and 52.219-2 and whether they are a manufacturer or dealer/distributor. The Air Force reserves the right to consider small business set-aside based on responses hereto. Requests for copies of this solicitation must be in writing; or fax (850) 882-9442. Telephone requests will not be honored. *****Note 22 (0099)

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