Goddard Space Flight Center, Code 216, Greenbelt, MD 20771

L -- IN-HOUSE ANALOG AND MIXED SIGNAL ASIC DESIGN FOR THE DEVELOPMENT OF HIGH CHANNEL DENSITY DETECTOR ARRAYS FOR ASTROHYSICAL RESEARCH. SOL RFQ5-80497 DUE 080696 POC Diane Scheuerman, Contracting Officer, 301-286-8086. Custom designs shall be performed with GSFC owned,CAE based ASIC design and simulation software. ASIC designs shall consist of multi-channel analog and digital circuits which will include charge sensitive amplifiers, shaping amplifiers, level discriminators, sample/hold circuits, analog multiplexer and associated ditital control logic circuits. Each channel shall be designed for optimal performance, when matched to specific detector capacitance, for low noise (typical input referenced noise of (200 E-), wide dynamic range ()1000), and low power ((300U watts/channel). The ASIC chip shall contain typically 32, 64, or 128 channels. The ASIC physical designs shall be based on 1.2 micrometers (or smaller) C-Mos technology. ASIC shall consist of prototype chips, fabricated through MOSIS. Flight chips shall be processed through qulified foundries. In-housed developed ASIC's performance shall be characterized and evaluated while integrated to cosmic photon and particle detectors. Performance criteria shall include but not limited to: charge collection efficiency, noise, speed, event dead time, design reliability, radiation hardness, power dissipation. Deliverable: The vendor shall design, develop, submit for fabrication, integrate and test at least two ASIC design, based on specific requirements defined by scientific objectives, detector characteristics, physical constraints, cost and scheudle. (0215)

Loren Data Corp. http://www.ld.com (SYN# 0066 19960805\L-0001.SOL)