Goddard Space Flight Center, Code 243, Greenbelt, MD 20771

70 -- NASA/GSFC INTENDS TO ENTER INTO A SOLE SOURCE CONTRACT WITH TO SHIBA CORPORATION FOR THE PURCHASE OF CARDS IMPLEMENTED ON TOSHIBA'S TC17OG7O. SOL RFP5-07779/037 POC Hasani Martin Skip Kemerer Contract Specialist Contracting Officer 301-286-7467 301-286-7244. NASA/GSFC intends to enter into a sole source contract with Toshiba Corporation for the purchase of cards implemented on Toshiba's TC17OG7O. This acquisition will be implemented pursuant to 10 U.S.C. 2304 (c)(1) -- only one responsible source. Toshiba is located in Wakefield, MA. The requirement includes the purchase of Layout Protype Parts Developement on TC17OG7O packaged in 160LFP. An option is included for the purchase of prototype parts packaged in ceramic, and prototype parts packaged in plastic. Design service will include insertion of boundary scan. The Chips which will be acquired were designed using Computer Aided Engineering (CAE) tools, Cadence and Synopsys. The Government has invested over $1M in these CAE tools, and has extensive in-house expertise in the use of these tools. Toshiba's development process is fully compatible with these CAE tools, therefore the Government does not require additional investments in CAE tools in the design and manufacture of its chips. Any vendor not using Candence, and Synopsys would require an additional investment in new CAE tools as well as extensive retraining of Government personnel. The Government requires high performance data system components to support existing programs. Toshiba is the only firm capable of providing this high performance with features that are unique to Toshiba. Toshiba provides gate array/standard cell sub-micron (.4 micron or better) technology, which implements very high density CMOS circuits capable of high performance with low power dissipation. In addition, Toshiba's new generation deep sub-micron gate array and embedded arrays offer highly accurate delay models, area- efficient memory cells, and very fine pitch TAB bonding capability for high I/O requirements. Toshiba has compatible, fully diffused large memory blocks, CPU cores such as Z80 and R3000. These features and capabilities are required to create high density low cost components within short design cycles. The Contractor shall also have the capability to produce packaging which includes: Dual In-Line Package (DIP), Plastic Bull Grid Array (PBGA), Plastic Quad Flat Pack (PQFP), Ceramic Quad Flat Pack (CQFP), Plastic Grid Array (PGA), Plastic Leadless ChipCarrier (PLCC), TAB Bonded (PQFP), Tape Carrier Package (TAB), Skinny DIP (SDIP). Toshiba's design environment shall support a variety of design for testability (DFT) methodologies including ATPG, full or partial scan, bounding scan (JTAG compliance with IEEE 1149.1), and built in self-test (BIST). Toshiba shall support several clock net type, including clock mesh, clock tree, clock grid, and clock trunck. Toshiba shall also support on board phase lock loop (PLL) circuitry for clock skew management. All responsible sources may respond to this synopsis by submitting a written narrative statement of capability, including detailed technical information and other technical literature, demonstrating the ability to meet the requirement. Also, submit any proposed cost which may be available. Responses must be submitted within 15 days of this notice to NASA/GSFC, Hasani Martin, Code 243, Greenbelt Rd., Greenbelt, MD 20771. All such responses will be fully considered. See Numbered Note(s): 12, 22. (0220)

Loren Data Corp. http://www.ld.com (SYN# 0291 19950809\70-0001.SOL)