SPECIAL NOTICE
99 -- Request for Information - DoD Design to Transition Accelerator
- Notice Date
- 5/17/2023 7:10:47 AM
- Notice Type
- Special Notice
- Contracting Office
- W6QK ACC-RI ROCK ISLAND IL 61299-0000 USA
- ZIP Code
- 61299-0000
- Response Due
- 6/30/2023 2:00:00 PM
- Point of Contact
- Kelli Senger
- E-Mail Address
-
kelli.k.senger.civ@army.mil
(kelli.k.senger.civ@army.mil)
- Description
- The Office of the Under Secretary of Defense for Research and Engineering (OUSD(R&E)) and the Office of the Under Secretary of Defense for Acquisition and Sustainment (OUSD(A&S)) are seeking information from the domestic microelectronics community to inform objectives for a DoD Design to Transition Accelerator (D2TA) (Figure 1) focused on leveraging commercial activities for microelectronics technology transitions (TRL 4-8) into DoD programs of record. The initiative seeks to reduce cost, schedule, and risk of deploying advanced electronics in DoD Programs of Record while optimizing warfighter system performance. The initiative is envisioned to leverage, for DoD use cases, best-in-class commercial Intellectual Property (IP), Electronic Design Automation (EDA) tools and practices, processes, device, package and board fabrication. Design center infrastructure is also envisioned to capture and retain design provenance across the full lifecycle to facilitate knowledge sharing and custom development expertise within the DoD ecosystem. OUSD(R&E) Trusted and Assured Microelectronics (T&AM) program funding will support design development and maturation activities using OUSD(A&S) Innovation Capability and Modernization (ICAM) Office funded electronics development infrastructure. Funding from Budget Activity (BA) 6.4 through 6.7 will start in FY24. This RFI requests input from a broad range of organizations, including academia, startups, small businesses, technology incubators, government labs, federally funded research and development centers (FFRDCs), University Applied Research Centers (UARCs), the defense industrial base (DIB), commercial Intellectual Property (IP) sources, Electronic Design Automation (EDA) companies, domestic semiconductor manufacturers and fabless chip design companies.� Please note that this RFI covers specific initiatives from T&AM and ICAM. Background U.S. technological dominance in ME materials, processes, devices, and architectural designs can only be sustained through the development of a robust domestic innovation ecosystem that fosters the rapid development and transition of novel concepts into commercially viable manufacturing processes. In recent years, U.S. chip innovation has been threatened as next-generation hardware technologies have become increasingly reliant on offshore sources for State of the Art (SOTA) as well as State of the Practice (SOTP) manufacturing, prototyping, and innovation. This trend creates significant hurdles for domestic microelectronics innovators. The dearth of development infrastructure -- from design phase through prototyping -- has resulted in a dramatic tapering of U.S. centric hardware startups/innovation.� The remaining U.S.-based technology startups have been forced to transition emerging microelectronics capabilities into off-shore ecosystems. To address these challenges, the DoD will pursue a multifaceted approach to strengthen the domestic microelectronics ecosystem.� The OUSD(R&E) Trusted and Assured Microelectronics (T&AM) program seeks to leverage domestic, commercial manufacturing and commercial designs / IP to provide DoD with cost-effective access to advanced technologies. Additionally, ICAM seeks to modernize internal DoD microelectronics development methodologies, accelerate implementation, and enable cost-effective sustainment for long-life DoD systems. Problem DoD must facilitate and promote the development of microelectronics prototypes (with demonstrable warfighter impact) sufficient for DoD program of record adoption and transition.� Current lines of effort often fall short on maturity or program relevance, and thus, require programs to absorb the cost and risk of maturation prior to desired transition. The result is three sequential �Valleys of Death� as illustrated in Figure 2. This effort addresses the second and third valleys where promising custom technologies do not align with program cost, schedule, and risk objectives, rendering them ill-suited for program adoption. We seek to construct a development process across OUSD R&E and OUSD A&S efforts capable of maturing custom microelectronics technologies to align with DoD Program of Record needs and constraints, specifically: Ability to address current and emerging warfighting threats on appropriate timelines. Performance and SWaP improvements that enable asymmetric warfighting advantage. Decrease cost to develop, field, and sustain electronics components and systems. Reduce risks for fielding new technologies and capabilities on schedule and in budget, specifically manufacturing maturity and integration readiness / compatibility. Solution Sought In order to inform a balanced investment strategy that prioritizes the transition of microelectronics across the supply chain, it is desirable for respondents to systematically categorize their input using a common framework.�Figure 3 is therefore proposed to encourage responses to address multiple dimensions of the microelectronics ecosystem (Figure 3 is included as an attachment). Dimension 1 � Supply Chain Segment(s).� The DEVICE and PACKAGING supply chain segments are centric to this RFI.� With that said, please address what segment(s) your response directly addresses.� Also, explain how you interface with the adjacent segments.� Highlight which provider tier best matches your organization and clearly describe your role in the supply chain ecosystem.� Elucidate how internal and external partnerships can accelerate technologies towards higher integration levels.� Identify challenges (e.g., gaps, fragmentations, uncertainties, etc.) opposing transition as well as solutions (e.g., disruptive technology, emerging markets, etc.) accelerating transition.� Lastly, feel free to critique the proposed supply chain segmentation (e.g., increasing resolution, adjusting phrasing, etc.). Dimension 2 � Technology Categories (by function). �High level technology categories are proposed:� Processing (Compute), RF/Millimeter Wave Spectrum, Optical Spectrum, and Power Delivery.� Please critique these proposed functions and propose subordinate categories per supply chain segment.� Provide perspective on priorities, gaps, etc.� How do these perspectives shape your technical and business approaches?� Explain how you see technical demonstration informing new requirements for the next supply chain segment. �Please avoid vagueness (e.g., state �RF GaN-on-Si� not �GaN� or �10kV� not �Medium Voltage�, etc.). �� Dimension 3 � Requirements.� Many cross-cutting requirements are proposed:� EDA tools, IP, Security (e.g., ITAR, Trust, Assurance), Workforce Development, Access, Self-Sustainability, Transition, etc.� Note � this list is not exhaustive, please feel free to critique and expand.� Please indicate whether requirements are specific to supply chain segments and technology categories by function.� These requirements/needs could potentially shape future contract elements. For the requirement(s) you are addressing, please also elaborate on the information and communication paths that must exist between and among DoD and relevant commercial organizations. For DEVICE and PACKAGING segment execution, it is envisioned that inputs from this RFI will result in consolidated custom electronics development best practices including: Early-cycle goal alignment and regular interlock between System Architecture, Subsystem Integration, Circuit Design, Device, Technology Integration, Materials Development, Manufacturing, and Test teams to negotiate features, performance, and schedule tradeoffs. Capture of development requirements into target specifications and target-based models for device design and Electronic System Level tradeoff analysis. Digital engineering / twin using modern EDA tools, simulation / emulation, and long-term provenance retention. Die-package-board-system co-design (ADKs, PDKs). Concurrent device hardware and software/firmware development, testing, and debug Domain specific architectures and languages to support multiple programs and commonality across programs. Continuous improvement in program execution Reuse and tailoring of IP cores to compose new designs Rigorous evaluation of device and process maturity (e.g., TRL and MRL assessments) �(D2TA) will leverage this design foundation to prepare and mature program-relevant microelectronic devices and designs including Application Specific Integrated Circuit (ASIC), custom packages, printed circuit boards, and subsystems that demonstrate warfighting advantage for DoD programs. Fabrication in relevant technologies is made available on predictable schedules to enable rapid realization of the components required for demonstration. The system must effectively capture and disseminate the microelectronics expertise acquired during development and maturation activities to enable rapid learning of practices and techniques to be shared broadly across the DoD workforce its programs. As the system evolves, it is envisioned that communities will form around specific DoD program use domains and define application programming interfaces (APIs) and Domain Specific Languages (DSL). �Once DoD specific processing needs and associated DSL�s are identified, the development system will construct and implement Domain Specific Architectures that leverage and extend commercial Intellectual Property that deliver order of magnitude improvement in performance and/or power. The system will capture DoD specific IP blocks and designs to enable common low-risk re-application to technology insertions and future programs.� The OUSD (R&E) and (A&S) D2TA will focus on critical, onshore prototyping for domain specific architectures for DoD sponsored demonstration and transition.� Key features are: Efforts that leverage, tailor, and, as appropriate, extend commercial designs and IP for DoD use cases. Government funded IP Development with favorable licensing rights. Secure IP repository, documentation, and maintenance with fine-grained access controls Capture and demonstration of promising R&D investment deliverables Will utilize existing domestic DoD/DIB microelectronics manufacturing infrastructure Envisioned D2TA System Elements Infrastructure: The custom development infrastructure must support commercial best practice Electronic Design Automation flows for ASICs, advanced packaging, and board development within a government Authorization to Operate (ATO) environment at IL-4/5 minimum. The infrastructure must support on-premise computational and test assets such as emulation hardware and device testers within the ATO boundary. The infrastructure must also support multiple sources of IP with access control based on licensure with cross-site traceability and provenance management capability. The infrastructure must provide a repository within the ATO boundary for persistent storage of design artifacts that comprise a digital thread of the accelerated development. D2TA Activities: The intent of the D2TA digital engineering activities is to select technical solutions, for which DoD acquisition programs have validated the transition potential and compose them into a program of record targeting a fully matured product for transition. Activities selected for acceleration must show direct program impact of the application of custom microelectronics up to the level of co-funding receiving program. Organizations participating in the acceleration effort include DIB contractors, commercial microelectronics service and product suppliers, small businesses, academia, non-profits, US Government entities and their direct contractors. These groups work together as a team to capture the knowledge developed during the acceleration effort within the DoD microelectronics ecosystem and ensure continued support for program integration. RFI Questions (Note: Reply only to relevant questions. Not necessary to reply to all) Supply Chain Positioning and Strategy In your business model, which step(s) of the supply chain outlined in Figure 3 does your organization align best with? What technology categories does your organization possess as core strengths (categories are not limited to those shown in Figure 3)? Describe the process used to manage your technology and development risks across supply-chain segments. What is the process nodes capability for production solutions of your organization (Legacy SOTP, SOTA)? How do you meet your quality requirements today? What kind of design flow do you have for design, fabrication, package, test, assembly Provide input of 3-DHI design flows and gaps What specific categories or segment-specific requirements in Figure 3 would your organization add to help clarify expectations in technology transitioning? What does your organization forecast the adoption rate of AI/ML to be in the immediate and medium term? Design Centers What does your organization consider key elements (software, infrastructure) of a successful custom microelectronics development system? How does your organization capture and disseminate best practices for custom microelectronics development? How many fabrications (State-of-the-Art, State-of-the-Practice, Legacy) does your organization participate in over the course of a year? What are the major barriers for accessing and maintaining licenses for third party IP? What are models for successful co-developed IP? What are some best practices for establishing Design Acceleration Centers to ensure flexibility and responsiveness to technology market needs and alignment with government and defense needs? What issues specific to the Design Acceleration Center concept should DoD consider when developing an approach to public-private partnerships? What are some best practices and recommendations for shared resources such as licenses for EDA tools? Models for self-sustained IP factories that provide enterprise government licensing and industry partners commercial rights? Technology Acceleration into Programs of Record How has your organization deployed custom microelectronics technologies into programs of record or commercial products? Please identify key operational domains that your organization believes will substantially benefit from custom microelectronics development. Does your organization have existing Intellectual Property that it would make available to DoD customers through some form or distribution model?� In contrast to commercial business operations, what gaps or barriers currently exist, in terms of access to information or communication channels, which hinder or prevent DoD business pursuits? How could a Design Accelerator help facilitate requirements communication between different entities in the supply chain? (i.e. between packaging and device entities, and between programs of record and device entities) What metrics do you impose on yourself to gauge success/failure of component transition to the subsystem segment of the supply chain? What criteria should be considered in identifying viable emerging technologies and new device and circuit concepts that are both sufficiently practical and also sufficiently high impact to warrant technology maturation and sustained interest by critical DIB and Commercial Industry partners? What terms is your organization willing to offer to DoD for license of internally developed Intellectual Property? Programs of Record are mandated to buy and field a capability, not piece part microelectronics, and often do not have the interest, bandwidth, or other means or resources to engage on such transition activities.� Describe your analysis and findings with respect to low transition of microelectronics technologies to programs of record, and offer recommendations of how the Department might improve it. RFI Submission and Contact Information This announcement is not a request for proposal submission. Any costs incurred by interested companies in response to this annoucement will NOT be reimbursed.� Responding to this RFI: Interested parties responding to this RFI must provide the following information: Company name Business size If your company is a small business, please identify an socio-economic category that applies CAGE code Name of primary point of contact for the response Email Phone number� All information received in response to this RFI may be marked ""Proprietary."" An email response will be sent after all data has been reviewed.� Responses can be provided in word format as a white paper not to exceed ten pages.� Responses will not be made public.� Please provide answers to the RFI Questions contained herein, and responses to this RFI must be submitted not later than 4PM on 30 June 2023.� RFI submissions will be accepted as email attachments only. All responses must be sent to the Agreement Specialist, Kelli Senger at kelli.k.senger.civ@army.mil with ""DoD Design to Transition Accelerator (D2TA) Response RFI"" in the subject line.��
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