SPECIAL NOTICE
R -- Digital Generation (DGEN) Subsystem Development and Integration (SDI) Prototype Project
- Notice Date
- 6/16/2020 12:22:42 PM
- Notice Type
- Special Notice
- NAICS
- 541512
— Computer Systems Design Services
- Contracting Office
- W6QK ACC-ORLANDO ORLANDO FL 32826-3224 USA
- ZIP Code
- 32826-3224
- Solicitation Number
- TREX-20-9-F007
- Response Due
- 7/17/2002 10:00:00 AM
- Archive Date
- 08/01/2002
- Point of Contact
- NSTXL
- E-Mail Address
-
initiatives@nstxl.org
(initiatives@nstxl.org)
- Description
- Digital Generation (DGEN) Subsystem Development and Integration (SDI) Prototype Project 16 June 2020 Purpose and Authority This Request for Solutions (RFS) is issued on behalf of Naval Air Warfare Systems Command (NAVAIR) who desires to identify and select capable vendors that can further advance its capabilities in the areas of electronic threat simulation and measurement focusing specifically on advances in the areas of system concept, architecture development, and requirements definition. The overall goal is to meet the increasingly critical needs for current and future Department of Defense (DOD) aircraft, which contain electronic combat support systems. To achieve this goal, NAVAIR is developing a new simulator program called NEWEG, which consists of a single configurable set of unclassified subsystems. The collection contains one Scenario Simulation and Control (SSC) subsystem, one or more DGEN subsystems, one or more Radio Frequency Generation (RFGEN) subsystems, and a Measurement and Analysis (MAA) subsystem. NEWEG is currently being developed in two Blocks: A and B. The DGEN system will be developed, demonstrated and assessed as part of Block B. The unclassified DGEN prototype project will focus on the continued development and testing of the DGEN subsystem. The objective of the DGEN SDI prototype project is to adapt and expand previous research, development, and initial proof-of-principle prototyping conducted by NAVAIR to date. The DGEN prototype project will design, develop, fabricate, assemble, integrate, and test variants of the initial proof-of-principle DGEN prototype capability. Specifically, the DGEN prototype project will develop and demonstrate specific aircraft, mission, and location tailored variants of NEWEG DGEN subsystem capabilities that will receive commands and data from the SSC and translate the simulated environment into a stream of Pulse Descriptor Words (PDW). The DGEN prototype will perform all pulse-to-pulse calculations required to generate a complex emitter environment in real-time for up to eight Million Pulses Per Second (MPPS). These calculations will include modeling the emitter waveform, applying the transmit antenna gain, and applying the radio frequency (RF) propagation, model. The emitter model will generate the PDW relative to the center of rotation of the System Under Test (SUT). In addition to creating PDWs, the DGEN prototype will also be responsible for recording and replaying the PDWs that it creates. Finally, the DGEN prototype will be required to stream third-party PDWs while generating PDWs internally. The tailored aircraft, mission, and location variant design and development tasks associated with the DGEN prototype project will be tested (demonstrated and assessed) with NEWEG systems at different DOD locations to include, but not limited to: (1) Air Station ASIL facility, Patuxent River NAS, MD, (2) Atlantic Test Range Facility, Patuxent River NAS, MD, (3) Benefield Anechoic Facility (BAF), Edwards AFB, CA, (4) Electronic Combat Simulation and Evaluation Laboratory, NBVC Pt. Mugu, CA, (5) Electronic Combat Range, NAS China Lake, CA, and (6) JPRIMES facility, Eglin AFB, FL. 2. Summary and Background 2.1 Overview The DGEN subsystem is responsible for describing a set of waveforms that will be received by a system under test (SUT) from many emitters in a simulated radio frequency (RF) environment. Emitters may be stationary or moving radars, communications, or other EW transmitters. The DGEN subsystem receives commands and data from the SSC according to the NEWEG Interface Design Description (IDD). It translates the programmed environment into digital pulse descriptor words (PDW) in a format specified by the DGEN-RFGEN Interface Control Document (ICD). It performs all pulse-to-pulse calculations required to generate a complex emitter environment in real-time (e.g., applying environmental, atmospheric, and other propagation effects and losses to each pulse). The DGEN handles the calculating and scheduling of pulsed descriptor waveforms for up to 8 million pulses per second (MPPS) for pulsed and modulations for non-pulsed signals by directly interpreting Electronic Warfare Integrated Reprogramming Database (EWIRDB) Standard EWIR Reference Format (SERF) and Waveform Descriptor Word (WDW) files. The DGEN calculates each PDW from the emitter to the SUT Center of rotation and transmits up to 8 MPPS to the RFGEN subsystem via an Ethernet fiber. The DGEN subsystem consists of an Electronic Industries Alliance (EIA) Standard 19 in electromagnetic interference (EMI) shielded cabinet housing, the Advanced Modular Pulsed Simulator (AMPS) Server(s), a field-programmable gate array (FPGA) board housed within each AMPS Server, interface and timing hardware, a data recorder, and an uninterruptable power supply.� Each AMPS has the processing capability to generate waveforms from non-reactive (Level-1) and reactive emitters (Level-2, -3) simultaneously. Level-1 emitters are modeled in real-time using the VIPER FPGA board and Level-2,-3 emitters are modeled in software using real-time Keystone. The AMPS Server is an end-to-end PDW generator that is capable of storing up to 5,000 emitters and modeling 1,024 Level-1 and 13 Level-2,-3 simultaneous emitters, and generating 2 MPPS with high-fidelity propagation effects. To reach higher emitter counts and pulse densities, AMPS units are stacked within the DGEN cabinet.� A complete AMPS unit consists of a server blade with a graphics-processing unit (GPU) and a VIPER FPGA board. The VIPER board is a standard Peripheral Component Interconnect Express (PCIe) board in the same form factor as a GPU. It contains a Xilinx Virtex-7 FPGA. It provides up to 12 10Gb Ethernet links. This board serves as the primary connection point to the RFGEN PDW bus. The DGEN system, because of its modularity, can be configured with a single AMPS system and can be extended up to 4 AMPS. This modularity allows a system�s emitter/pulse density to increase through the addition of these AMPS and minor cabling. Another optional DGEN capability is antenna port processing. Currently, DGEN itself calculates the parameters of the received RF pulse at a single SUT reference point. By adding another server, that response can be extended out to every SUT antenna port. Note, this server is simply the AMPS server configured with different software and firmware. Primary DGEN operation is done through the SSC. The only user interface with the DGEN subsystem is via the Standalone Controller GUI. This GUI is a Web page connected to a Web server available on the DGEN subsystem. The Web server hosts HTTP/HTTPS services in sync with current HTTP/HTTPS standards, and the user requests a Web page, which is served by the RTI Web Integration Service. The RTI Web Integration service executes on the Master AMPS server.� The communication architecture is based on Data Distribution Service (DDS) Publish and Subscribe paradigm, where the data writers are used to publish data, and data readers are used to subscribing to data. To establish communication with the DGEN subsystem, the Web server is integrated with DDS. 3.�Training and Readiness Accelerator (TReX) Vendors interested in responding to this RFS must be members of TReX or teamed with a TReX member.� Information about membership can be found on the following webpage: https://nstxl.org/membership/.� This project will be managed and supervised by the Integrated Battlespace Simulation and Testing (IBST) program management team. ***Please visit the TReX RFS website for additional information, at: https://nstxl.org/opportunity/digital-generation-dgen-subsystem-development-and-integration-sdi-prototype-project/
- Web Link
-
SAM.gov Permalink
(https://beta.sam.gov/opp/f3fbb21fc7cf4dfb8dfa5229ea678f24/view)
- Place of Performance
- Address: USA
- Country: USA
- Country: USA
- Record
- SN05692119-F 20200618/200616230202 (samdaily.us)
- Source
-
SAM.gov Link to This Notice
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