SPECIAL NOTICE
66 -- Notice of Intent to Award Sole Source
- Notice Date
- 8/9/2018
- Notice Type
- Special Notice
- NAICS
- 334413
— Semiconductor and Related Device Manufacturing
- Contracting Office
- Department of Commerce, National Institute of Standards and Technology (NIST), NIST AMD Boulder, 325 Broadway, Boulder, Colorado, 80305, United States
- ZIP Code
- 80305
- Solicitation Number
- NB672030-18-02037
- Archive Date
- 8/30/2018
- Point of Contact
- Michael G. Fredericks, Phone: 3034977763, Michael George Fredericks,
- E-Mail Address
-
michael.fredericks@nist.gov, mikefred56@aol.com
(michael.fredericks@nist.gov, mikefred56@aol.com)
- Small Business Set-Aside
- N/A
- Description
- FEDBIZOPPS.GOV ANNOUNCEMENT: SUBJECT: Notice of intent to award a Sole Source SOLICITATION NUMBER: NB672030-18-02037, Integrated Circuit Kit and Consultation CONTACT POINTS: Michael Fredericks, Contracting Officer (303) 497-7763; DESCRIPTION: The National Institute of Standards and Technology (NIST) Acquisition Management Division, on behalf of the Applied Physics Division (686), intends to issue a Firm Fixed Priced purchase order to a single source under the authority of FAR 13.106-1, "Only One Responsible Source" and no other supplies or services will satisfy agency requirements, to Teledyne Scientific & Imaging, LLC, Cage Code 2D609, 1049 Camino Dos Rios, Thousand Oaks, CA. for Integrated Circuit Kit and Consultation Specifications: General: The circuits will be based on InP HBT transistors capable of producing power amplifiers with 0.5 mW of output power at 585 GHz and 20 dB of small signal gain at 650 GHz, mixers, phase-locked loops, dynamic frequency dividers, and oscillators. The substrate is semi-insulating InP with a 100 orientation or other suitable electro-optic material, and should be polished on the back side to allow electro-optic sampling through the back of the substrate. The back of the substrate should also be clean and suitable for deposition of anti-reflective coatings at NIST. It must be possible to form coplanar waveguide (CPW) transmission lines on the top surface of the substrate and to remove semi- conducting epitaxy (epi) layers under the CPW to reduce substrate losses in the CPW. The technology must also support thin-film microstrip transmission lines on the top surface in BCB or similar low-loss low-dielectric-constant insulators suitable for fabricating broadband combiners and other passive microstrip circuitry that operate up to 650 GHz. The conductors on the top surface of the wafer must be robust enough to allow wire bonding, on-wafer probing, and solder connections. New designs resulting from this effort will remain confidential property of NIST. Item 1. Design kit and consultation. Vendor will provide circuit libraries to NIST with a complete set of transistor designs, electrical models and corresponding layouts. If the vendor technology is different than the130 nm and 250 nm InP HBT technology offered by Teledyne Scientific and previously used at NIST, NIST will provide the vendor with the previous NIST designs, and provide guidance on the circuit functionality and expected performance. The vendor will be responsible for adjusting NIST designs to meet the NIST-required performance, and then transferring the updated designs into their technology process. The existing NIST circuits subject to modification are high frequency power amplifiers, active load-pull circuitry, high frequency comb generators, high-frequency signal sources and electro-optic sampling components required in the construction of a millimeter-wave LSNA and high-frequency comb generators. Vendor will provide NIST with their corresponding designs, layouts and electrical models. Models and layouts will be applicable to circuit designs spanning the frequency range of 25 GHz to 650 GHz targeted here in the newer 130 nm node from Teledyne Scientific. Any design kits and design layouts will be provided in the Keysight Advanced Design System. Item 2. Integrated circuit fabrication. Vendor will fabricate integrated circuits as designed by NIST with design assistance from the vendor using their standard foundry technology and deliver approximately 20 unpackaged integrated-circuit chips from each fabrication run to NIST. The anticipated size of the integrated-circuit chips will be approximately 6 mm2. If the vendor provides an alternative technology to the Teledyne Scientific technology previously used at NIST, the translated test structures will have to provide equal or better performance than simulated. The North American Industry Classification System (NAICS) code for this acquisition is 334413, (Semiconductor and Related Device Manufacturing), size standard 1250. No solicitation package will be issued. This Notice of Intent is NOT a Request for Quotation (RFQ) nor is it a request for competition; however, interested parties may identify their interest and capability to respond to the requirement. Inquiries will only be accepted via e-mail to michael.fredericks@nist.gov. The government will consider responses received no later than 2pm, MDT, Wednesday, 15 August 2018. Interested parties that believe they could satisfy the requirements listed above for NIST may clearly and unambiguously identify their capability to do so in writing on or before the response date for this notice. Any prospective contractor must be registered in the System for Award Management (SAM) to be eligible for award. Information concerning SAM registered requirements may be viewed via the Internet at http://sam.gov. Written responses to this synopsis shall contain sufficient documentation to establish a bona fide capability to fulfill the requirement. A determination by the Government not to compete this proposed requirement based upon responses to this notice is solely within the discretion of the Government. Information received will normally be considered solely for determining whether to conduct a competitive procurement in the future. No telephone requests will be honored. Any questions regarding this notice must be submitted in writing via email to Michael Fredericks at michael.fredericks@nist.gov.
- Web Link
-
FBO.gov Permalink
(https://www.fbo.gov/notices/770ed6872fcc0225bd3337312c763445)
- Place of Performance
- Address: NIST, 325 Broadway, Boulder, Colorado, 80831, United States
- Zip Code: 80831
- Record
- SN05029748-W 20180811/180809231421-770ed6872fcc0225bd3337312c763445 (fbodaily.com)
- Source
-
FedBizOpps Link to This Notice
(may not be valid after Archive Date)
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