SOURCES SOUGHT
66 -- Foundry Fabrication Services
- Notice Date
- 1/19/2018
- Notice Type
- Sources Sought
- NAICS
- 333242
— Semiconductor Machinery Manufacturing
- Contracting Office
- Department of Commerce, National Institute of Standards and Technology (NIST), Acquisition Management Division, 100 Bureau Drive, Building 301, Room B130, Gaithersburg, Maryland, 20899-1410, United States
- ZIP Code
- 20899-1410
- Solicitation Number
- AMD-SS18-06
- Archive Date
- 2/17/2018
- Point of Contact
- Forest Crumpler, Phone: 3019756753
- E-Mail Address
-
forest.crumpler@nist.gov
(forest.crumpler@nist.gov)
- Small Business Set-Aside
- N/A
- Description
- NIST CNST is seeking responsible parties to supply foundry fabrication services for microdevices. We are specifically looking for respondents capable of economically developing, implementing and providing low-volume microfabrication of silicon based photonic micro electro mechanical devices according to NIST design and specifications. The minimum capabilities are as follows: 1.Ability to use high resolution optical lithography and dry etch to pattern 200 nm to 300 nm thick silicon on insulator layer (SOI) on 200 mm (or larger) diameter silicon wafers a.Minimum lateral feature size is 150 nm for dense silicon lines and spaces and 120 nm for isolated silicon lines. b.Commercial 193nm lithography tool or equivalent patterning technology at 200 mm wafer size or larger is required because the work is to develop and demonstrate feasibility of future commercial manufacturing of the devices. c.Wafer patterning by e-beam lithography is explicitly excluded. d.Patterning should produce smooth sidewalls with roughness at least below 10 nm for high performance Si photonic resonators 2.Ability to transfer the pattern into SOI Si layer (200 nm to 300 nm) with smooth and vertical side walls, e.g. via an appropriate dry etch process, wafer-scale. 3.Ability to deposit high quality silicon dioxide layer at least 1 um thick. 4.Ability to deposit pinhole-free silicon nitride layer at least 200 nm thick. 5.Ability to pattern (aligned to the Si pattern) and etch the silicon nitride layer a.Nitride should be cleared b.Overetch into oxide not exceeding 300 nm. c.Pattern dimensions >10 um d.Alignment accuracy ~1um or less 6.Ability to pattern (aligned to Si or nitride pattern) and etch through Nitride, Oxide, SOI, buried oxide (2um thick) to the substrate a.All layers should be removed b.Pattern dimensions >10um c.Alignment accuracy ~1um The performer is expected to conduct one or more experiments to verify the SOI patterning and provide devices to NIST for testing. The performer then is expected to conduct experiments as necessary to implement the full fabrication sequence and provide 2 to 5 wafers of fabricated devices to NIST for further processing and testing. NIST is seeking responses from all responsible sources, including large, foreign, and small businesses. Small businesses are defined under the associated NAICS code for this effort, 333242, as those domestic sources having 1,500 employees or less. Please include your company's size classification and socio-economic status in any response to this notice. Companies that can provide the required foundry services are requested to email a detailed response describing their abilities to Forest.crumpler@nist.gov no later than the response date for this sources sought notice. The response should include achievable specifications and any other information relevant to your product or capabilities. Point of Contact Forest Crumpler, Contracting Officer, Phone (301) 975-6753, Fax (301) 975-8753, Email forest.crumpler@nist.gov
- Web Link
-
FBO.gov Permalink
(https://www.fbo.gov/spg/DOC/NIST/AcAsD/AMD-SS18-06/listing.html)
- Place of Performance
- Address: 100 Bureau Drive, Gaithersburg, Maryland, 20899, United States
- Zip Code: 20899
- Zip Code: 20899
- Record
- SN04794392-W 20180121/180119230827-0da3eab4441a17a1b57be5adbbfee00b (fbodaily.com)
- Source
-
FedBizOpps Link to This Notice
(may not be valid after Archive Date)
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