SPECIAL NOTICE
99 -- TECHNOLOGY TRANSFER OPPORTUNITY - SELF-SCRUBBING TECHNOLOGY FORRECONFIGURABLE RAD-HARD MEMORY ARRAYS
- Notice Date
- 1/20/2012
- Notice Type
- Special Notice
- NAICS
- 927110
— Space Research and Technology
- Contracting Office
- NASA/Langley Research Center, Mail Stop 12, Industry Assistance Office, Hampton,VA 23681-0001
- ZIP Code
- 23681-0001
- Solicitation Number
- TTO0952
- Archive Date
- 1/20/2013
- Point of Contact
- Sean Sullivan, Media Specialist, Phone 757-864-5055, Fax 757-864-8101, Email sean.d.sullivan@nasa.gov
- E-Mail Address
-
Sean Sullivan
(sean.d.sullivan@nasa.gov)
- Small Business Set-Aside
- N/A
- Description
- NASA Langley Research Center in Hampton, VA solicits interest from companiesinterested in obtaining license rights to commercialize, manufacture and market thefollowing technology. License rights may be issued on an exclusive or nonexclusive basisand may include specific fields of use. THE TECHNOLOGY: NASA Langley has developed a firmware approach to mitigating single event upsets (SEUs)in radiation-tolerant field programmable gate arrays (FPGAs), including configurationmemory, clock management, and configuration logic. Since this technology can beimplemented within an FPGA, there is no need for the additional external hardwarecurrently required for SEU mitigation, thus lowering cost, weight, and power; decreasingcomplexity; and improving reliability. NASA Langley has developed the technology forhigh-performance space-based computing applications. The technology has been tested andwill be used on an instrument on NASAs Mars Science Laboratory rover, scheduled forlaunch in 2009.NASA developed the technology to meet the needs for on-board satellite data processingfor future missions. The continuing trends toward ever-increasing resolution, improveddata quality, and additional capacity for raw and/or processed data will necessitate theuse of larger on-board memories, which must be made radiation tolerant. This technologyis a firmware approach to radiation-tolerant memory, suitable for both GEO and LEOmissions.Memory cells in FPGAs are susceptible to SEUs. It is important to correct configurationmemory upset as quickly as possible. NASA has used an approach of refreshing theconfiguration memory cells at regular intervals. The configuration bit stream is storedin memory and upon power-on, the FPGA loads its configuration from memory. The memoryrefresh controller is implemented internally in the FPGA. The correction of SEUs inconfiguration logic requires initial detection of a failure in configuration logic, whichhas also been developed and incorporated as part of this technology.In addition to detecting SEUs, the technology implements a scrubbing strategy where thememory contents are read sequentially and when an error is detected, the memory isupdated with correct data.To express interest in this opportunity, please respond to Sean Sullivan, ResearchTriangle International (RTI), at: NASA Langley Research Center, Strategic RelationshipsOffice (SRSO),17 West Taylor St., Mail Stop 218, Building 1212, Room 110 Hampton,Virginia, E-mail: Sean.D.Sullivan@NASA.gov, or phone: 757-864-5055. Please indicate thedate and title of the FBO notice and include your company and contact information.RTI is responsible for aggregating and acknowledging all responses. These responses areprovided to members of NASA Langleys Innovative Partnerships Office within the SRO forthe purpose of promoting public awareness of our technology products, and conductingpreliminary market research to determine public interest in and potential for futurelicensing opportunities. If direct licensing interest results from this posting, SRO willfollow the formal licensing process of posting in the Federal Register as required. Nofollow-on procurement is expected to result from responses to this Notice.
- Web Link
-
FBO.gov Permalink
(https://www.fbo.gov/spg/NASA/LaRC/OPDC20220/TTO0952/listing.html)
- Record
- SN02658473-W 20120122/120120234740-0a304fdd509310b083e81634abaa80bc (fbodaily.com)
- Source
-
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