SPECIAL NOTICE
A -- Energy Efficient Cryogenic Memory
- Notice Date
- 6/17/2011
- Notice Type
- Special Notice
- NAICS
- 541712
— Research and Development in the Physical, Engineering, and Life Sciences (except Biotechnology)
- Contracting Office
- Office of the Director of National Intelligence, Intelligence Advanced Research Projects Activity, Washington, District of Columbia, 20511, United States
- ZIP Code
- 20511
- Solicitation Number
- IARPA-RFI-11-01
- Archive Date
- 7/6/2012
- Point of Contact
- Marc Manheimer,
- E-Mail Address
-
dni-iarpa-rfi-11-01@ugov.gov
(dni-iarpa-rfi-11-01@ugov.gov)
- Small Business Set-Aside
- N/A
- Description
- Synopsis The Intelligence Advanced Research Projects Activity (IARPA) often selects its research efforts through the Broad Agency Announcement (BAA) process. This request for information (RFI) is intended to provide information relevant to a possible future IARPA program, so that feedback from potential participants can be considered prior to the issuance of a BAA. Respondents are invited to provide comments on the content of this announcement to include suggestions for improving the scope of a possible solicitation to ensure that every effort is made to adequately address the scientific and technical challenges described below. Additionally, responses to this request may be used to inform a one-day workshop (explained below). Therefore, responses to this RFI must be available for unrestricted public distribution, and hence proprietary material should not be included in responses. The following sections of this announcement contain details of the scope of technical efforts of interest, along with instructions for the submission of responses. Background The goal is to develop memory technologies that will enable high performance computing systems with greatly improved energy efficiency. Computing systems based on single flux quantum (SFQ) logic are of interest for their potential to provide both lower energy per operation and higher speed relative to CMOS. SFQ logic is based on pulses generated by Josephson junctions with quantized flux 0 = 2.07 mVps. Pulses are typically of magnitude ~1 mV and duration ~1 ps. Variants of SFQ logic include: rapid single flux quantum (RSFQ), efficient single flux quantum (eSFQ) and reciprocal quantum logic (RQL). In addition to logic, computing systems require memory and interconnects. An intermediate term goal is a 10-100 GHz, 32-bit, 1-million gate processor with at least 1 MiB of local memory integrated on a multi-chip module (MCM). High performance computing systems need significant quantities of memory in close proximity to the logic circuits. Systems based on SFQ logic are currently hampered by the lack of compatible cache (on-chip) and main memory (on-chip or off-chip, but still physically close) of sufficiently low energy dissipation, high speed, and high density. Practical SFQ logic implementations currently require the use of low temperature superconductors in the Josephson junction switching elements and typically must operate at temperatures below 10 K. Memory is needed that can operate in the 4-10 K temperature range, preferably on the logic chips. SFQ logic pulses are low voltage (~1 mV) and contain very little energy. Amplifying SFQ logic pulses to drive memories can require significant time, energy and circuitry. In general, the less amplification required, the more compatible the memory. Superconductive memories based on flux quanta are compatible with SFQ logic, but have not yet achieved sufficiently high area density. The fabrication technology used to produce a memory affects compatibility with SFQ logic circuits. Fabrication technologies for SFQ logic currently are expected to have the following general characteristics: •Technology Node: 250 to 90 nm •superconducting material: Nb •superconducting layers: 8-12 (most planarized) •compatible with CMOS back-end-of-line fabrication processes in most cases •Josephson junction critical current density: 10-50 kA/cm2, < 5% spread (1 sigma) Memory of different types may be needed to balance requirements for energy efficiency, speed, density, and cost. The memory hierarchy typically includes register, cache and main memory. Register memory is within the data path. Cache memory may be subdivided in a hierarchy such as Level 1 (L1) and Level 2 (L2) with L1 cache memory being the fastest. Memory directly on the CPU chip may include some or all of the cache memories. Memory technologies suitable for use as cache or main memories are of interest. Candidates for cache or main memory elements should have read/write energies in the 10-17 to 10-19 joule range, with read/write times in the low nanosecond range or better. Main memories that operate above 4 K are also of interest, with relaxed energy requirements given the reduced cooling overhead. The initial memory density target is for 108 bits/cm2 with the expectation of an order of magnitude improvement over time or better. Access latency for memory that includes decoding and addressing should be ten clock cycles or less (@10 GHz clock). The above numbers represent rough initial goals, and cryogenic memories will need to exceed these goals for eventual success of a program to develop superconducting computing. Information on memories that meet or exceed these goals is especially welcome. Ideas for which these numbers have not been determined are nevertheless encouraged with the expectation that good estimates could be established within a year's time, as are ideas that do not meet these goals initially but for which it is anticipated that a clear path to improvement, given a modest level of effort, is possible within a year. Scope Information is requested about memory technologies compatible with SFQ logic chips. Memory that can be fabricated on the same chip and operable using the mV-level signals produced by SFQ Josephson junction logic circuits is preferred but is not required. Information requested here would, at a minimum, address the following questions: •What is the physical basis of the memory element? •What is the evidence that the memory elements will operate in the 4-10 K temperature range necessary for compatibility with SFQ logic circuits? •Is fabrication compatible with SFQ logic, or would separate chips be required? •How would the memory interface with the mV-level signals typical in SFQ circuits? •Including interface circuits, what read and write times (latency and throughput) are expected? •What energy dissipation is expected per read and write? •How is the energy dissipation expected to scale with the amount of memory (number of bits)? •What is the timescale needed to demonstrate these solutions? •What are the compelling advantages? •What challenges are foreseen? •What resources are needed? •Are supporting technologies available? The responses to this RFI will be used to help in the planning of a one-day workshop. The selection of topics, participants, and setting of the agenda of this workshop will in part be informed by the responses, with responders potentially being invited to participate and present at this workshop. The results of this workshop may justify a competitive program. It is anticipated that this workshop will be held on or about 19 July 2011. Preparation Instructions to Respondents IARPA solicits respondents to submit ideas related to this topic for use by the Government in formulating a potential program. IARPA requests that submittals briefly and clearly describe the potential approach or concept, outline critical technical issues, and comment on the expected performance, robustness, and estimated cost of the proposed approach. This announcement contains all of the information required to submit a response. No additional forms, kits, or other materials are needed. IARPA appreciates responses from all capable and qualified sources from within and outside of the US. Because IARPA is interested in an integrated approach, responses from teams with complementary areas of expertise are encouraged. Responses have the following formatting requirements: 1.A one page cover sheet that identifies the title, organization(s), respondent's technical and administrative points of contact - including names, addresses, phone numbers, and email addresses of all co-authors, and clearly indicating its association with IARPA-RFI-11-01; 2.A substantive, focused, one-half page executive summary; 3.A description (limited to 5 pages in minimum 12 point Times New Roman font, appropriate for single-sided, single-spaced 8.5 by 11 inch paper, with 1-inch margins) of the technical challenges and suggested approach(es); 4.A list of citations (any significant claims or reports of success must be accompanied by citations, and reference material MUST be attached); 5.Optionally, a single overview briefing chart graphically depicting the key ideas. Submission Instructions to Respondents Responses to this RFI are due no later than 4:00pm, Local Time, College Park, MD on 5 July 2011. All submissions must be electronically submitted to DNI-IARPA-RFI-11-01@ugov.gov as a PDF document. Inquiries to this RFI must be submitted to DNI-IARPA-RFI-11-01@ugov.gov. Do not send questions with proprietary content. No telephonic inquiries will be accepted. DISCLAIMERS AND IMPORTANT NOTES This is an RFI issued solely for information and new program planning purposes and does not constitute a solicitation. Respondents are advised that IARPA is under no obligation to acknowledge receipt of the information received, or provide feedback to respondents with respect to any information submitted under this RFI. Responses to this notice are not offers and cannot be accepted by the Government to form a binding contract. Respondents are solely responsible for all expenses associated with responding to this RFI. It is the respondents' responsibility to ensure that the submitted material has been approved for public release by the organization that funded whatever research is referred to in their response. The Government does not intend to award a contract on the basis of this RFI or to otherwise pay for the information solicited, nor is the Government obligated to issue a solicitation based on responses received. Neither proprietary nor classified concepts or information should be included in the submittal. Input on technical aspects of the responses may be solicited by IARPA from non-Government consultants/experts who are bound by appropriate non-disclosure requirements.
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